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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF40373B MSI Octal transparent latch with 3-state outputs
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Octal transparent latch with 3-state outputs
DESCRIPTION The HEF40373B is an 8-bit transparent latch with 3-state buffered outputs. The output stages have high current output capability suitable for driving highly capacitive loads. The latch outputs follow the data inputs when the latch enable (E) is HIGH. When E is LOW, the data that meets the set-up times is latched. The 3-state outputs are controlled by the output enable input EO. A HIGH on
HEF40373B MSI
EO causes the outputs to assume a high impedance OFF-state. The device features hysteresis on the E input to improve noise rejection. Schmitt-trigger action in the E input makes the circuit highly tolerant to slower input rise and fall times. The HEF40373B is pin and functionally compatible with the TTL `373' device. Supply voltage range: 3 to 15 V.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING HEF40373BP(N): 20-lead DIL; plastic (SOT146-1) HEF40373BD(F): HEF40373BT(D): 20-lead DIL; ceramic (cerdip) (SOT152) 20-lead SO; plastic (SOT163-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category MSI See Family Specifications D0 to D7 E EO O0 to O7 data inputs latch enable input output enable input (active LOW) 3-state buffered outputs
January 1995
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Octal transparent latch with 3-state outputs HEF40373B MSI
Product specification
Philips Semiconductors
Product specification
Octal transparent latch with 3-state outputs
FUNCTION TABLE INPUTS OPERATING MODES EO enable & read register latch & read register latch register & disable outputs Notes 1. H = HIGH state (the more positive voltage) h = HIGH state (one set-up time prior to the HIGH-to-LOW enable transition) L = LOW state (the less positive voltage) I = LOW state (one set-up time prior to the HIGH-to-LOw enable transition) Z = high impedance OFF-state L L L L H H E H H L L L L Dn L H I h I h INTERNAL REGISTER L H L H L H
HEF40373B MSI
OUTPUTS O0 TO O7 L H L H Z Z
January 1995
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Philips Semiconductors
Product specification
Octal transparent latch with 3-state outputs
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) See Family Specifications, except for: D.C. current into any input D.C. source or sink current into any output D.C. current into the supply terminals DC CHARACTERISTICS VSS = 0 V VDD V VOH V VOL V SYMBOL Tamb (C) -40 MIN. Output current HIGH Output current HIGH Output current LOW Hysteresis voltage at enable input (E) 5 10 15 5 10 15 5 10 15 5 10 15 VH 4,6 9,5 13,5 3,6 8,4 13,2 0,4 0,5 1,5 IOL -IOH -IOH 0,75 1,85 14,5 9,3 14,4 19,5 2,9 9,5 30,0 TYP. + 25 MIN. 0,6 1,5 15 10 15 20 2,3 7,6 25 TYP. 1,2 3,0 50 24 46 62 5,4 17 45 220 250 320 II IO I max. max. max.
HEF40373B MSI
10 mA 25 mA 100 mA
+ 85 MIN. 0,45 1,1 15,5 10,7 15,0 19,8 1,75 5,50 19,0 TYP. mA mA mA mA mA mA mA mA mA mV mV mV
(1) P-channel MOS transistor conducting. (2) P-channel MOS transistor and bipolar n-p-n transistor conducting.
Fig.5 Typical output source current characteristic.
Fig.6 Schematic diagram of output stage.
January 1995
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Philips Semiconductors
Product specification
Octal transparent latch with 3-state outputs
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays E On HIGH to LOW E On LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 3-state propagation delays Output disable times EO On HIGH 5 10 15 5 LOW Output enable times EO On HIGH 5 10 15 5 LOW Set-up time Dn E Hold time Dn E Minimum latch enable pulse width LOW 10 15 5 10 15 5 10 15 5 10 15 tWEL thold tsu 15 10 10 25 15 10 60 30 20 tPZL tPZH 65 30 25 85 35 25 7 5 5 15 4 3 30 15 10 130 60 50 170 70 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 15 tPLZ tPHZ 65 30 25 75 40 30 130 60 50 150 80 60 ns ns ns ns ns ns 5 10 15 5 10 15 5 10 15 5 10 15 tTLH tTHL tPLH tPHL 150 60 40 125 50 40 40 20 15 30 20 15 300 120 80 250 100 80 80 40 30 60 40 30 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX.
HEF40373B MSI
TYPICAL EXTRAPOLATION FORMULA 138 ns + (0,24 ns/pF) CL 59 ns + (0,01 ns/pF) CL 36 ns + (0,07 ns/pF) CL 122 ns + (0,06 ns/pF) CL 48 ns + (0,03 ns/pF) CL 39 ns + (0,02 ns/pF) CL
see Fig.7
January 1995
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Philips Semiconductors
Product specification
Octal transparent latch with 3-state outputs
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 3 325 fi + (foCL) x VDD2 14 200 fi + (foCL) x VDD
2
HEF40373B MSI
where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
37 425 fi + (foCL) x VDD2
tTLH - - - - tTHL
Fig.7 Output transition times as a function of the load capacitance. .
January 1995
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